RISC-V is a groundbreaking CPU instruction set architecture. Along with being an open-source instruction set, RISC-V is informed by decades of industry experience with various RISC processor designs, while being unencumbered with the necessity of backward compatibility. It is a unique opportunity to base a processor design on sound engineering principles, & the successful applicant will have comprehensive daily hands-on exposure to this architecture. While several companies are pursuing RISC-V design, only SiFive is founded & actively run by the inventors of RISC-V. This is not an academic exercise; we have real customers & real silicon.
SiFive is looking for hardware engineers who are passionate about designing industry-leading CPU & interconnect IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications. We're creating massively customizable IP & improving time-to-market by designing hardware as highly-configurable generators. We're using technology & ideas from the software industry to execute hardware design with the agility of software development.
We build & maintain multiple CPU lines, TileLink interconnects & other uncore/infrastructure IP using the Chisel hardware construction library embedded in the Scala language, & are seeking motivated individuals to improve/evolve our existing IP as well as develop new IP.
Join us, & surf the RISC-V wave with SiFive!