Responsibilities: 
  Architect, design & implement new features, performance improvements, & ISA extensions in RISC-V CPU core generators. 
  Microarchitecture development & specification. Ensure that knowledge is shared via great documentation & participation in a culture of collaborative design. 
  Perform initial sandbox verification, & work with design verification team to create & execute thorough verification test plans. 
  Work with physical implementation team to implement & optimize physical design to meet frequency, area, power goals. 
  Collaborate with performance modelling team for performance exploration & optimization to meet performance goals. 

Requirements: 

  8+ yrs of recent industry experience in high-performance, energy-efficient CPU designs. 
  Expertise in CPU processor designs in one or more of the following areas: instruction fetch & decode; branch prediction; register renaming & instruction scheduling; scalar and/or vector execution units; load-store unit; cache & memory subsystems. 
  Knowledge of RISC-V architecture is a plus. 
  Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL. 
  Experience with Scala and/or Chisel is a plus. 
  Attention to detail & a focus on high-quality design. 
  Ability to work well with others & a belief that engineering is a team sport. 
  Knowledge of at least one object-oriented and/or functional programming language. 
  Background of successful CPU development from architecture through tapeout.

  MS/ PhD degree in EE, CE, CS or a related technical discipline, or equivalent experience.