Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry & have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities & impact on AI industry?

Were looking forward to you joining us to collaborate, contribute, & revolutionize AI silicon & system.

Description 

We are looking for a world-class Memory Subsystem Architect to join our SoC team at Baidus Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive in this highly technical environment. Your job responsibilities as a Memory Subsystem Architect will be providing technical leadership through all phases of Baidus AI SoC development, but primarily focused on unified memory space architecture design for Baidu AI accelerator SoC. The working goal is to build unified memory space for thousands of accelerators from user's perspective.

Developing architecture & micro-architecture to improve the state-of-the-art AI SoC memory system. Explore & evaluate the architectural design choices in SoC fabrics, system caches, system coherency, & MMUs.

Work with software & SoC design team to define architecture & build unified memory space system across distributed AI training system.

Work with Hardware design, verification, emulation, & validation teams to build & test the hardware architecture, performance & functionality.

Participate in performance simulation of features to improve memory subsystem efficiency. Analyzing benchmarks, application workloads & performance simulation results to identify areas for microarchitecture optimizations.

Debug performance & functional issues with high-level models, RTL simulation, & silicon.

Qualifications

• 10+ years of experience in Silicon architecture or IP design mainly focusing on memory subsystem.
• Strong understanding of distributed AI training system's requirement on SoC memory subsystem.
• Demonstrated experience in HW digital design & understanding of CPU/HW Accelerators and/or Peripheral design.
• Familiarity with SW & Operating system practices & requirements on memory system.
• Experience in System Performance analysis & debug in pre and/or Post-Silicon environments.
• Solid background of System interconnect, System MMUs, Caches & Memory Technologies (e.g. HBM, GDDR, DDR & LPDDR4/5).
• Experience with data analysis using Excel, Perl, Python etc.
• Master or PhD in Electrical or Computer Engineering.
• Excellent communication skills in both English & Chinese.

Culture Fit:

• Mission alignment: If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
• Self-directed: We work best with people that are driven, motivated, & aspire to greatness.
• Hungry to learn: We are eager to see you learn new skills & grow.
• Team orientation: We work in small, fast-moving teams. We watch out for each other & go after big goals together as a team.