SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. SEMICONDUCTOR AND PACKAGING ENGINEER
In this role, you will be responsible for packaging design, development & new product introduction You will work with multi-functional teams & drive package integration efforts, package & enabling technology development. A major part of the role includes leading OSATs toward wafer & chip scale packaging processes, including setting & documenting package specifications & design rules, assembly process troubleshooting, new assembly technology development, managing yield & ramp toward NPI & volume production.
- Manage, develop & transfer high yielding advanced packaging solutions for volume production & lead risk mitigation strategies for critical areas of assembly
- Conduct & approve packaging proposals, designs, schematics, process flows, risk assessments, technical specifications, reliability requirements, data collection, & analysis
- Drive IC packaging initiatives from product qualification to high volume ramp for next generation devices
- Collaborate with foundry & OSAT suppliers to define process flow, process control, tool qualifications to enable high volume manufacturing
- Define & implement new packaging design & process capabilities through generating or updating ECN controlled documentation such as process control & design rule documents
- Design new package technologies incorporating new materials & process development to provide high thermal & high reliability solutions for micro-module packaging
- Develop & implement design rules & other specifications for the new technologies & designs & manage the new product introduction (including product reliability testing, manufacturing risk assessment) at the assembly factories
- Generate required data & documentation for the fabrication, assembly & customer application data sheets of the new package technology
- Bachelor's degree in electrical engineering, mechanical engineering, physics, or material science
- 5+ years working with bumping, TSV, RIE, CVD, & CMP processes
- 5+ years working with packaging materials, structures, process development & their interactions
PREFERRED SKILLS AND EXPERIENCE:
- Master's degree
- Thorough understanding of packaging design, manufacturing & component materials
- Experience in 2D/2.5D/3D packaging design with Cadence (SIP, Virtuoso, & or Innovous) or equivalent
- Good understating of JEDEC methodology for component level & board level reliability qualification requirements
- Familiarity with packaging, latest reliability & fault isolation methods/principle
- Detailed understanding of all major wafer, chip & board-level packaging processes, including advanced packaging techniques
- Strong IC packaging materials background including characterization & failure analysis
- Program management skills
- To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence & qualifications & will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceXs Affirmative Action Plan for veterans & individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.