SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
PRINCIPAL SOC PHYSICAL DESIGN STA/TIMING ENGINEER (SILICON ENGINEERING)
As a member of our multifaceted ASIC team, you will have the rare & phenomenal opportunity to craft upcoming SOCs that will enable our Starlink chips. These chips help connect, enable, & empower humanity every single day with performance that far surpasses that of traditional satellite internet & ground infrastructure limitations. Starlink delivers high-speed, low latency broadband internet to locations where access has been unreliable, expensive, or completely unavailable.
In this critical role, as an SOC/ASIC back-end static timing analysis (STA) engineer, you will be collaborating with architecture, timing, & logic design teams making a crucial impact on delivering cutting edge SOCs for customers on Earth & beyond. We are looking for people who want to dive in & get their hands dirty & push the limits of what is possible through innovation, determination, & teamwork.
- Develop/support automated block & full chip level advanced timing/noise signoff flows (with advanced & parametric on chip variation, & voltage drop aware STA)
- Define block & full chip timing signoff criterion, methodology, constraints, modes & scenarios & close timing at multi-corner & multi-mode environments
- Develop/support signoff STA timing/power optimization engineering change order flows & integrate them into physical design flow
- Work with systems & architecture, SOC integration, verification, DFT, mixed signal, IP owners, synthesis, & place/route teams to address the design challenges in the context of timing sign-off
- Generate block timing begets, clock & I/O context files
- Debug & drive fixing of constraint correlation issues between top & block level
- Develop clock network simulation & jitter analysis methodologies
- Drive custom IP integration, custom timing check flow enablement & closure until tapeout
- Guide full chip team to plan & build reference/special clock trees for minimal jitter & insertion delay
- Develop & run block/full chip level noise analysis flows & drive the noise/signal integrity closure with block & full chip engineers
- Work with voltage drop, architecture, package teams to understand voltage drops, guard banding requirements, voltage & library selection for signoff STA & noise analysis
- Bachelors degree in electrical engineering, computer engineering or computer science
- 10+ years experience creating static timing analysis flows for SOC/ASICs
PREFERRED SKILLS AND EXPERIENCE:
- Full chip & block level STA tapeout experience, constraint generation & partitioning
- Knowledge of deep sub-micron FinFET technology nodes (7nm & below) timing challenges, multi-corner & multimode timing closure, process variations, voltage drop aware STA, & clock reconvergence pessimism removal
- Experience in IP integration (e.g. memories, I/Os, Analog IPs, SerDes, DDR etc.)
- Experience in industry standard STA & Noise/Signal integrity analysis tools
- Experience in clock jitter simulation & analysis methodologies
- Experience with clock domain crossings, DFT/Scan/MBIST/LBIST & understanding of their impact on physical design & timing closure
- Deep understanding of ASIC synthesis & physical design flows & methodologies
- Experience with high reliability design & implementations
- Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile, etc.)
- Familiar with implementation or integration of design blocks using Verilog/System Verilog
- Self-driven individual with a can-do attitude, & an ability to work in a dynamic group environment
- Must be willing to travel when needed (typically <10%)
- To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence & qualifications & will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceXs Affirmative Action Plan for veterans & individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.